Design a finite state machine (FSM) for a system that gives output high when bit-1 is in the majority in a three-bit number (overlapping is allowed), assuming the input is coming serially. The FSM should have the following states
A) State A: No bits received, State B: Bit-1 received, State C: Bit-0 received after receiving Bit-1
B) State A: No bits received, State B: Bit-0 received, State C: Bit-1 received after receiving Bit-0
C) State A: No bits received, State B: Bit-1 received, State C: Bit-0 received after receiving Bit-1, State D: Bit-1 received after receiving Bit-0
D) State A: No bits received, State B: Bit-1 received, State C: Bit-0 received after receiving Bit-1, State D: Bit-0 received after receiving Bit-1